Digital counters having a large component count currently are used in integrated circuit and other circuit applications. Such counters may be referred to as high bit-count counters. Typically, they are used for timeout counters or timers in a variety of different applications. Some such applications include the timing of various functions in real time computer operation.
In order to test the accuracy of high bit-count digital counters, the counters should be operated through the entire range of counts capable of implementation by such counters. To test a counter having a large number of stages in real time, however, consumes an extremely large amount of tester time. This is particularly true if the counter must be operated in a normal mode, since the counter clock for a normal mode of operation generally is at a lower frequency than higher frequencies which are available in some test modes of operation.
Efforts have been made to shorten the time required for testing large multi-stage counters by segmenting the counter stages into different groups and then testing the groups in parallel with one another. Parallel testing of the counters within each group then significantly reduces the testing time, but fails to test the interface or connections between the different groups within the counter. Thus, it is possible for errors to exist in the interfaces, which are not tested by such a system. Failure to detect such errors may result in the incorporation of a flawed counter into a finished product. This type of testing is called a fixed division scheme, which cannot fully test a counter because, with the exception of the least significant bit of the counter, the least significant bits of each divided section of the counter cannot be tested.
To fully test large bit-count multi-stage counters, systems have been designed to employ two fixed division schemes to ensure testing of the interface or connections between the segments. In such a system, two test modes are employed. The first test mode is used for testing the portion of the interface connections between the segments. After this first portion of the test has been run, a switchover to the second test mode is made to complete the testing of the remainder of the counter and interfaces. While this type of system permits parallel testing of the stages of the counters in different groups of equal numbers of stages, time is wasted in the tester during the switching over from one test mode to the other test mode.
A system which has been designed to accelerate counter testing without the loss of fault coverage is disclosed in the Moughanni U.S. Pat. No. 5,402,458. The system of this counter divides the counter into a number of different segments, each having an equal number of bits or stages. The system operates to detect when each segment nears the last count and overrides the test mode to re-enable a between segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between segments on the next clock cycle. While this system theoretically functions to test all of the stages, as well as the interface connections between the different segments of the counter, a test of these connections from one segment to the next is only effective from a cycle of "0" to "1". The system cannot test between segments where the count changes from "1" to "0" in the interface. As a consequence, while the Moughanni system overcomes many of the disadvantages of the prior art, an incomplete test results from this inherent weakness in the interconnections between the different segments of the counter undergoing a test with the system of Moughanni. The Moughanni system does operate to produce a rapid test of the counter with a relatively low number of clock cycles (S-2)+2.sup.b clock cycles where S is the number of segments and b is the number of bits or stages per segment.
It is desirable to provide a system and method for testing digital counters which eliminates switchover time between the testing of different blocks and which fully tests all of the toggle nodes of the counter for a complete, rapid, efficient test.